目录 Preface9 ChapterbyChapter Summary15 PART ONE SOLIDSTATE ELECTRONICS AND DEVICES CHAPTER 1 INTRODUCTION TO ELECTRONICS3 1.1A Brief History of Electronics: From Vacuum Tubes to GigaScale Integration7 1.2Classication of Electronic Signals10 1.2.1Digital Signals11 1.2.2Analog Signals11 1.2.3A/D and D/A Converters—Bridging the Analog and Digital Domains12 1.3Notational Conventions14 1.4ProblemSolving Approach15 1.5Important Concepts from Circuit Theory17 1.5.1Voltage and Current Division17 1.5.2Thévenin and Norton Circuit Representations18 1.6Frequency Spectrum of Electronic Signals23 1.7Ampliers24 1.7.1Ideal Operational Ampliers25 1.7.2Amplier Frequency Response27 1.8Element Variations in Circuit Design28 1.8.1Mathematical Modeling of Tolerances28 1.8.2WorstCase Analysis29 1.8.3Monte Carlo Analysis31 1.8.4Temperature Coefcients34 1.9Numeric Precision36 Summary36 Key Terms37 References38 Additional Reading38 Problems38 深入理解微电子电路设计 目录 CHAPTER 2 SOLIDSTATE ELECTRONICS45 2.1SolidState Electronic Materials49 2.2Covalent Bond Model50 2.3Drift Currents and Mobility in Semiconductors53 2.3.1Drift Currents53 2.3.2Mobility54 2.3.3Velocity Saturation54 2.4Resistivity of Intrinsic Silicon55 2.5Impurities in Semiconductors56 2.5.1Donor Impurities in Silicon57 2.5.2Acceptor Impurities in Silicon57 2.6Electron and Hole Concentrations in Doped Semiconductors57 2.6.1nType Material(ND >NA)58 2.6.2pType Material(NA>ND )59 2.7Mobility and Resistivity in Doped Semiconductors60 2.8Diffusion Currents64 2.9Total Current65 2.10Energy Band Model66 2.10.1Electron—Hole Pair Generation in an Intrinsic Semiconductor66 2.10.2Energy Band Model for a Doped Semiconductor67 2.10.3Compensated Semiconductors67 2.11Overview of Integrated Circuit Fabrication69 Summary72 Key Terms73 References74 Additional Reading74 Problems74 CHAPTER 3 SOLIDSTATE DIODES AND DIODE CIRCUITS80 3.1The pn Junction Diode83 3.1.1 pn Junction Electrostatics83 3.1.2Internal Diode Currents87 3.2The iv Characteristics of the Diode88 3.3The Diode Equation: A Mathematical Model for the Diode90 3.4Diode Characteristics under Reverse, Zero, and Forward Bias93 3.4.1Reverse Bias93 3.4.2Zero Bias93 3.4.3Forward Bias94 3.5Diode Temperature Coefcient96 3.6Diodes under Reverse Bias96 3.6.1Saturation Current in Real Diodes97 3.6.2Reverse Breakdown99 3.6.3Diode Model for the Breakdown Region100 3.7 pn Junction Capacitance100 3.7.1Reverse Bias100 3.7.2Forward Bias101 3.8Schottky Barrier Diode103 3.9Diode SPICE Model and Layout103 3.9.1Diode Layout104 3.10Diode Circuit Analysis105 3.10.1LoadLine Analysis106 3.10.2Analysis Using the Mathematical Model for the Diode107 3.10.3The Ideal Diode Model111 3.10.4Constant Voltage Drop Model113 3.10.5Model Comparison and Discussion114 3.11MultipleDiode Circuits115 3.12Analysis of Diodes Operating in the Breakdown Region118 3.12.1LoadLine Analysis118 3.12.2Analysis with the Piecewise Linear Model118 3.12.3Voltage Regulation119 3.12.4Analysis Including Zener Resistance120 3.12.5Line and Load Regulation121 3.13HalfWave Rectier Circuits122 3.13.1HalfWave Rectier with Resistor Load122 3.13.2Rectier Filter Capacitor123 3.13.3HalfWave Rectier with RC Load124 3.13.4Ripple Voltage and Conduction Interval125 3.13.5Diode Current127 3.13.6Surge Current129 3.13.7PeakInverseVoltage (PIV) Rating129 3.13.8Diode Power Dissipation129 3.13.9HalfWave Rectier with Negative Output Voltage130 3.14FullWave Rectier Circuits132 3.14.1FullWave Rectier with Negative Output Voltage133 3.15FullWave Bridge Rectication133 3.16Rectier Comparison and Design Tradeoffs134 3.17Dynamic Switching Behavior of the Diode138 3.18Photo Diodes, Solar Cells, and LightEmitting Diodes139 3.18.1Photo Diodes and Photodetectors139 3.18.2Power Generation from Solar Cells140 3.18.3LightEmitting Diodes (LEDs)141 Summary142 Key Terms143 Reference144 Additional Reading144 Problems144 CHAPTER 4 FIELDEFFECT TRANSISTORS156 4.1Characteristics of the MOS Capacitor159 4.1.1Accumulation Region160 4.1.2Depletion Region161 4.1.3Inversion Region161 4.2The NMOS Transistor161 4.2.1Qualitative iv Behavior of the NMOS Transistor162 4.2.2Triode Region Characteristics of the NMOS Transistor163 4.2.3On Resistance166 4.2.4Transconductance167 4.2.5Saturation of the iv Characteristics168 4.2.6Mathematical Model in the Saturation (PinchOff)Region169 4.2.7Transconductance in Saturation170 4.2.8ChannelLength Modulation170 4.2.9Transfer Characteristics and DepletionMode MOSFETs171 4.2.10Body Effect or Substrate Sensitivity173 4.3PMOS Transistors174 4.4MOSFET Circuit Symbols176 4.5Capacitances in MOS Transistors179 4.5.1NMOS Transistor Capacitances in the Triode Region179 4.5.2Capacitances in the Saturation Region180 4.5.3Capacitances in Cutoff180 4.6MOSFET Modeling in SPICE181 4.7MOS Transistor Scaling182 4.7.1Drain Current183 4.7.2Gate Capacitance183 4.7.3Circuit and Power Densities183 4.7.4PowerDelay Product184 4.7.5Cutoff Frequency184 4.7.6High Field Limitations185 4.7.7The Unied MOS Transistor Model Including High Field Limitations186 4.7.8Subthreshold Conduction187 4.8MOS Transistor Fabrication and Layout Design Rules188 4.8.1Minimum Feature Size and Alignment Tolerance188 4.8.2MOS Transistor Layout188 4.9Biasing the NMOS FieldEffect Transistor192 4.9.1Why Do We Need Bias?192 4.9.2FourResistor Biasing194 4.9.3Constant GateSource Voltage Bias198 4.9.4Graphical Analysis for the QPoint198 4.9.5Analysis Including Body Effect198 4.9.6Analysis Using the Unied Model201 4.10Biasing the PMOS FieldEffect Transistor202 4.11The Junction FieldEffect Transistor (JFET)204 4.11.1The JFET with Bias Applied205 4.11.2JFET Channel with DrainSource Bias207 4.11.3 nChannel JFET iv Characteristics207 4.11.4The pChannel JFET209 4.11.5Circuit Symbols and JFET Model Summary209 4.11.6JFET Capacitances210 4.12JFET Modeling in Spice210 4.13Biasing the JFET and DepletionMode MOSFET211 Summary214 Key Terms216 References216 Problems217 CHAPTER 5 BIPOLAR JUNCTION TRANSISTORS231 5.1Physical Structure of the Bipolar Transistor234 5.2The Transport Model for the npn Transistor235 5.2.1Forward Characteristics236 5.2.2Reverse Characteristics238 5.2.3The Complete Transport Model Equations for Arbitrary Bias Conditions239 5.3The pnp Transistor241 5.4Equivalent Circuit Representations for the Transport Models243 5.5The iv Characteristics of the Bipolar Transistor244 5.5.1Output Characteristics244 5.5.2Transfer Characteristics245 5.6The Operating Regions of the Bipolar Transistor245 5.7Transport Model Simplications246 5.7.1Simplied Model for the Cutoff Region247 5.7.2Model Simplications for the ForwardActive Region249 5.7.3Diodes in Bipolar Integrated Circuits255 5.7.4Simplied Model for the ReverseActive Region256 5.7.5Modeling Operation in the Saturation Region258 5.8Nonideal Behavior of the Bipolar Transistor261 5.8.1Junction Breakdown Voltages262 5.8.2MinorityCarrier Transport in the Base Region262 5.8.3Base Transit Time263 5.8.4Diffusion Capacitance265 5.8.5Frequency Dependence of the CommonEmitter Current Gain266 5.8.6The Early Effect and Early Voltage266 5.8.7Modeling the Early Effect267 5.8.8Origin of the Early Effect267 5.9Transconductance268 5.10Bipolar Technology and SPICE Model269 5.10.1Qualitative Description269 5.10.2SPICE Model Equations270 5.10.3HighPerformance Bipolar Transistors271 5.11Practical Bias Circuits for the BJT272 5.11.1FourResistor Bias Network274 5.11.2Design Objectives for the FourResistor Bias Network276 5.11.3Iterative Analysis of the FourResistor Bias Circuit280 5.12Tolerances in Bias Circuits280 5.12.1WorstCase Analysis281 5.12.2Monte Carlo Analysis283 Summary286 Key Terms288 References288 Problems289 PART TWO DIGITAL ELECTRONICS CHAPTER 6 INTRODUCTION TO DIGITAL ELECTRONICS303 6.1Ideal Logic Gates307 6.2Logic Level Denitions and Noise Margins307 6.2.1Logic Voltage Levels309 6.2.2Noise Margins309 6.2.3Logic Gate Design Goals310 6.3Dynamic Response of Logic Gates311 6.3.1Rise Time and Fall Time311 6.3.2Propagation Delay312 6.3.3PowerDelay Product312 6.4Review of Boolean Algebra313 6.5NMOS Logic Design315 6.5.1NMOS Inverter with Resistive Load316 6.5.2Design of the W/L Ratio of MS317 6.5.3Load Resistor Design318 6.5.4LoadLine Visualization318 6.5.5OnResistance of the Switching Device320 6.5.6Noise Margin Analysis321 6.5.7Calculation of VIL and VOH321 6.5.8Calculation of VIH and VOL322 6.5.9Resistor Load Inverter Noise Margins322 6.5.10Load Resistor Problems323 6.6Transistor Alternatives to the Load Resistor324 6.6.1The NMOS Saturated Load Inverter325 6.6.2NMOS Inverter with a Linear Load Device333 6.6.3NMOS Inverter with a DepletionMode Load334 6.7NMOS Inverter Summary and Comparison337 6.8Impact of Velocity Saturation on Static Inverter Design338 6.8.1Switching Transistor Design338 6.8.2Load Transistor Design338 6.8.3Velocity Saturation Impact Summary339 6.9NMOS NAND and NOR Gates339 6.9.1NOR Gates340 6.9.2NAND Gates341 6.9.3NOR and NAND Gate Layouts in NMOS DepletionMode Technology342 6.10Complex NMOS Logic Design343 6.11Power Dissipation348 6.11.1Static Power Dissipation348 6.11.2Dynamic Power Dissipation349 6.11.3Power Scaling in MOS Logic Gates350 6.12Dynamic Behavior of MOS Logic Gates351 6.12.1Capacitances in Logic Circuits352 6.12.2Dynamic Response of the NMOS Inverter with a Resistive Load353 6.12.3Comparison of NMOS Inverter Delays358 6.12.4Impact of Velocity Saturation on Inverter Delays359 6.12.5Scaling Based upon Reference Circuit Simulation359 6.12.6Ring Oscillator Measurement of Intrinsic Gate Delay360 6.12.7Unloaded Inverter Delay360 6.13PMOS Logic363 6.13.1PMOS Inverters363 6.13.2NOR and NAND Gates365 Summary366 Key Terms368 References369 Additional Reading369 Problems369 CHAPTER 7 COMPLEMENTARY MOS(CMOS)LOGIC DESIGN383 7.1CMOS Inverter Technology386 7.1.1CMOS Inverter Layout388 7.2Static Characteristics of the CMOS Inverter388 7.2.1CMOS Voltage Transfer Characteristics389 7.2.2Noise Margins for the CMOS Inverter391 7.3Dynamic Behavior of the CMOS Inverter393 7.3.1Propagation Delay Estimate393 7.3.2Rise and Fall Times395 7.3.3Performance Scaling395 7.3.4Impact of Velocity Saturation on CMOS Inverter Delays397 7.3.5Delay of Cascaded Inverters398 7.4Power Dissipation and Power Delay Product in CMOS399 7.4.1Static Power Dissipation399 7.4.2Dynamic Power Dissipation400 7.4.3PowerDelay Product401 7.5CMOS NOR and NAND Gates403 7.5.1CMOS NOR Gate403 7.5.2CMOS NAND Gates406 7.6Design of Complex Gates in CMOS407 7.7Minimum Size Gate Design and Performance413 7.8Cascade Buffers415 7.8.1Cascade Buffer Delay Model415 7.8.2Optimum Number of Stages416 7.9The CMOS Transmission Gate418 7.10Bistable Circuits419 7.10.1The Bistable Latch419 7.10.2RS FlipFlop422 7.10.3The DLatch Using Transmission Gates423 7.10.4A MasterSlave D FlipFlop423 7.11CMOS Latchup423 Summary428 Key Terms429 References430 Problems 430 CHAPTER 8 MOS MEMORY CIRCUITS442 8.1RandomAccess Memory (RAM)445 8.1.1RandomAccess Memory (RAM)Architecture445 8.1.2A 256MB Memory Chip446 8.2Static Memory Cells447 8.2.1Memory Cell Isolation and Access— the 6T Cell447 8.2.2The Read Operation448 8.2.3Writing Data into the 6T Cell452 8.3Dynamic Memory Cells454 8.3.1The 1T Cell455 8.3.2Data Storage in the 1T Cell455 8.3.3Reading Data from the 1T Cell457 8.3.4The 4T Cell458 8.4Sense Ampliers460 8.4.1A Sense Amplier for the 6T Cell460 8.4.2A Sense Amplier for the 1T Cell462 8.4.3The Boosted Wordline Circuit463 8.4.4Clocked CMOS Sense Ampliers464 8.5Address Decoders466 8.5.1NOR Decoder466 8.5.2NAND Decoder466 8.5.3PassTransistor Column Decoder468 8.6ReadOnly Memory (ROM)469 8.7Flash Memory472 8.7.1Floating Gate Technology472 8.7.2NOR Circuit Implementations475 8.7.3NAND Implementations475 Summary477 Key Terms478 References479 Problems 479 CHAPTER 9 BIPOLAR LOGIC CIRCUITS487 9.1The Current Switch (EmitterCoupled Pair)490 9.1.1Mathematical Model for Static Behavior of the Current Switch490 9.1.2Current Switch Analysis for vI > VREF492 9.1.3Current Switch Analysis for vI < VREF493 9.2The EmitterCoupled Logic (ECL) Gate493 9.2.1ECL Gate with vI = VH494 9.2.2ECL Gate with vI = VL495 9.2.3Input Current of the ECL Gate495 9.2.4ECL Summary495 9.3Noise Margin Analysis for the ECL Gate496 9.3.1VIL, VOH , VIH , and VOL496 9.3.2Noise Margins497 9.4Current Source Implementation498 9.5The ECL ORNOR Gate500 9.6The Emitter Follower502 9.6.1Emitter Follower with a Load Resistor503 9.7“Emitter Dotting” or “WiredOR” Logic505 9.7.1Parallel Connection of EmitterFollower Outputs506 9.7.2The WiredOR Logic Function506 9.8ECL PowerDelay Characteristics506 9.8.1Power Dissipation506 9.8.2Gate Delay508 9.8.3PowerDelay Product509 9.9Positive ECL (PECL)510 9.10Current Mode Logic510 9.10.1CML Logic Gates511 9.10.2CML Logic Levels512 9.10.3 VEE Supply Voltage512 9.10.4HigherLevel CML513 9.10.5CML Power Reduction514 9.10.6SourceCoupled Fet Logic (SCFL)514 9.11The Saturating Bipolar Inverter517 9.11.1Static Inverter Characteristics517 9.11.2Saturation Voltage of the Bipolar Transistor518 9.11.3LoadLine Visualization520 9.11.4Switching Characteristics of the Saturated BJT521 9.12TransistorTransistor Logic (TTL)524 9.12.1TTL Inverter Analysis for vI = VL524 9.12.2Analysis for vI = VH526 9.12.3Power Consumption527 9.12.4TTL Propagation Delay and Power Delay Product527 9.12.5TTL Voltage Transfer Characteristic and Noise Margins528 9.12.6Fanout Limitations of Standard TTL528 9.13Logic Functions in TTL528 9.13.1MultiEmitter Input Transistors529 9.13.2TTL NAND Gates529 9.13.3Input Clamping Diodes530 9.14SchottkyClamped TTL531 9.15Comparison of the PowerDelay Products of ECL and TTL532 9.16BiCMOS Logic532 9.16.1BiCMOS Buffers533 9.16.2BiNMOS Inverters535 9.16.3BiCMOS Logic Gates536 Summary537 Key Terms538 References539 Additional Reading539 Problems 539 PART THREE ANALOG ELECTRONICS CHAPTER 10 ANALOG SYSTEMS AND IDEAL OPERATIONAL AMPLIFIERS553 10.1An Example of an Analog Electronic System556 10.2Amplication557 10.2.1Voltage Gain558 10.2.2Current Gain559 10.2.3Power Gain559 10.2.4The Decibel Scale560 10.3TwoPort Models for Ampliers563 10.3.1The gParameters563 10.4Mismatched Source and Load Resistances567 10.5Introduction to Operational Ampliers570 10.5.1The Differential Amplier570 10.5.2Differential Amplier Voltage Transfer Characteristic571 10.5.3Voltage Gain571 10.6Distortion in Ampliers574 10.7Differential Amplier Model575 10.8Ideal Differential and Operational Ampliers577 10.8.1Assumptions for Ideal Operational Amplier Analysis577 10.9Analysis of Circuits Containing Ideal Operational Ampliers578 10.9.1The Inverting Amplier579 10.9.2The Transresistance Amplier—a CurrenttoVoltage Converter582 10.9.3The Noninverting Amplier584 10.9.4The UnityGain Buffer, or Voltage Follower586 10.9.5The Summing Amplier589 10.9.6The Difference Amplier591 10.10Frequency Dependent Feedback593 10.10.1Bode Plots594 10.10.2The LowPass Amplier594 10.10.3The HighPass Amplier597 10.10.4BandPass Ampliers600 10.10.5An Active LowPass Filter603 10.10.6An Active HighPass Filter607 10.10.7The Integrator608 10.10.8The Differentiator611 Summary612 Key Terms613 References614 Additional Reading614 Problems614 CHAPTER 11 NONIDEAL OPERATIONAL AMPLIFIERS AND FEEDBACK AMPLIFIER STABILITY627 11.1Classic Feedback Systems630 11.1.1ClosedLoop Gain Analysis631 11.1.2Gain Error631 11.2Analysis of Circuits Containing Nonideal Operational Ampliers632 11.2.1Finite OpenLoop Gain632 11.2.2Nonzero Output Resistance635 11.2.3Finite Input Resistance639 11.2.4Summary of Nonideal Inverting and Noninverting Ampliers643 11.3Series and Shunt Feedback Circuits644 11.3.1Feedback Amplier Categories644 11.3.2Voltage Ampliers—SeriesShunt Feedback645 11.3.3Transimpedance Ampliers—ShuntShunt Feedback645 11.3.4Current Ampliers—ShuntSeries Feedback645 11.3.5Transconductance Ampliers—Series Series Feedback645 11.4Unied Approach to Feedback Amplier Gain Calculation645 11.4.1ClosedLoop Gain Analysis646 11.4.2Resistance Calculations Using Blackman’s Theorem646 11.5SeriesShunt Feedback—Voltage Ampliers646 11.5.1ClosedLoop Gain Calculation647 11.5.2Input Resistance Calculations647 11.5.3Output Resistance Calculations648 11.5.4SeriesShunt Feedback Amplier Summary649 11.6ShuntShunt Feedback—Transresistance Ampliers653 11.6.1ClosedLoop Gain Calculation653 11.6.2Input Resistance Calculations654 11.6.3Output Resistance Calculations654 11.6.4ShuntShunt Feedback Amplier Summary655 11.7SeriesSeries Feedback—Transconductance Ampliers658 11.7.1ClosedLoop Gain Calculation659 11.7.2Input Resistance Calculation659 11.7.3Output Resistance Calculation660 11.7.4SeriesSeries Feedback Amplier Summary660 11.8ShuntSeries Feedback—Current Ampliers662 11.8.1ClosedLoop Gain Calculation663 11.8.2Input Resistance Calculation663 11.8.3Output Resistance Calculation664 11.8.4ShuntSeries Feedback Amplier Summary664 11.9Finding the Loop Gain Using Successive Voltage and Current Injection667 11.9.1Simplications670 11.10Distortion Reduction through the Use of Feedback670 11.11dc Error Sources and Output Range Limitations671 11.11.1InputOffset Voltage671 11.11.2OffsetVoltage Adjustment673 11.11.3InputBias and Offset Currents674 11.11.4Output Voltage and Current Limits676 11.12CommonMode Rejection and Input Resistance679 11.12.1Finite CommonMode Rejection Ratio679 11.12.2Why Is CMRR Important?680 11.12.3VoltageFollower Gain Error due to CMRR683 11.12.4CommonMode Input Resistance686 11.12.5An Alternate Interpretation of CMRR687 11.12.6Power Supply Rejection Ratio687 11.13Frequency Response and Bandwidth of Operational Ampliers689 11.13.1Frequency Response of the Noninverting Amplier691 11.13.2Inverting Amplier Frequency Response694 11.13.3Using Feedback to Control Frequency Response696 11.13.4LargeSignal Limitations—Slew Rate and FullPower Bandwidth698 11.13.5Macro Model for Operational Amplier Frequency Response699 11.13.6Complete Op Amp Macro Models in SPICE700 11.13.7Examples of Commercial General Purpose Operational Ampliers700 11.14Stability of Feedback Ampliers701 11.14.1The Nyquist Plot701 11.14.2FirstOrder Systems702 11.14.3SecondOrder Systems and Phase Margin703 11.14.4Step Response and Phase Margin704 11.14.5ThirdOrder Systems and Gain Margin707 11.14.6Determining Stability from the Bode Plot708 Summary712 Key Terms714 References714 Problems 715 CHAPTER 12 OPERATIONAL AMPLIFIER APPLICATIONS729 12.1Cascaded Ampliers732 12.1.1TwoPort Representations732 12.1.2Amplier Terminology Review734 12.1.3Frequency Response of Cascaded Ampliers737 12.2The Instrumentation Amplier745 12.3Active Filters748 12.3.1LowPass Filter748 12.3.2A HighPass Filter with Gain752 12.3.3BandPass Filter754 12.3.4Sensitivity756 12.3.5Magnitude and Frequency Scaling757 12.4SwitchedCapacitor Circuits758 12.4.1A SwitchedCapacitor Integrator758 12.4.2Noninverting SC Integrator760 12.4.3SwitchedCapacitor Filters762 12.5DigitaltoAnalog Conversion765 12.5.1D/A Converter Fundamentals765 12.5.2D/A Converter Errors766 12.5.3DigitaltoAnalog Converter Circuits768 12.6AnalogtoDigital Conversion772 12.6.1A/D Converter Fundamentals773 12.6.2AnalogtoDigital Converter Errors774 12.6.3Basic A/D Conversion Techniques775 12.7Oscillators786 12.7.1The Barkhausen Criteria for Oscillation786 12.7.2Oscillators Employing Frequency Selective RC Networks787 12.8Nonlinear Circuit Applications791 12.8.1A Precision HalfWave Rectier791 12.8.2Nonsaturating PrecisionRectier Circuit792 12.9Circuits Using Positive Feedback794 12.9.1The Comparator and Schmitt Trigger794 12.9.2The Astable Multivibrator796 12.9.3The Monostable Multivibrator or One Shot797 Summary801 Key Terms803 Additional Reading804 Problems 804 CHAPTER 13 SMALLSIGNAL MODELING AND LINEAR AMPLIFICATION818 13.1The Transistor as an Amplier821 13.1.1The BJT Amplier822 13.1.2The MOSFET Amplier823 13.2Coupling and Bypass Capacitors824 13.3Circuit Analysis Using dc and ac Equivalent Circuits826 13.3.1Menu for dc and ac Analysis826 13.4Introduction to SmallSignal Modeling830 13.4.1Graphical Interpretation of the Small Signal Behavior of the Diode830 13.4.2SmallSignal Modeling of the Diode831 13.5SmallSignal Models for Bipolar Junction Transistors833 13.5.1The HybridPi Model835 13.5.2Graphical Interpretation of the Transconductance836 13.5.3SmallSignal Current Gain836 13.5.4The Intrinsic Voltage Gain of the BJT837 13.5.5Equivalent Forms of the SmallSignal Model838 13.5.6Simplied Hybrid Pi Model839 13.5.7Denition of a Small Signal for the Bipolar Transistor839 13.5.8SmallSignal Model for the pnp Transistor841 13.5.9ac Analysis versus Transient Analysis in SPICE842 13.6The CommonEmitter (CE) Amplier842 13.6.1Terminal Voltage Gain842 13.6.2Input Resistance844 13.6.3Signal Source Voltage Gain844 13.7Important Limits and Model Simplications844 13.7.1A Design Guide for the CommonEmitter Amplier845 13.7.2Upper Bound on the CommonEmitter Gain846 13.7.3SmallSignal Limit for the Common Emitter Amplier846 13.8SmallSignal Models for FieldEffect Transistors849 13.8.1SmallSignal Model for the MOSFET849 13.8.2Intrinsic Voltage Gain of the MOSFET851 13.8.3Denition of SmallSignal Operation for the MOSFET852 13.8.4Body Effect in the FourTerminal MOSFET853 13.8.5SmallSignal Model for the PMOS Transistor854 13.8.6SmallSignal Model for the Junction FieldEffect Transistor855 13.9Summary and Comparison of the SmallSignal Models of the BJT and FET856 13.10The CommonSource Amplier859 13.10.1CommonSource Terminal Voltage Gain860 13.10.2Signal Source Voltage Gain for the CommonSource Amplier860 13.10.3A Design Guide for the Common Source Amplier860 13.10.4SmallSignal Limit for the Common Source Amplier861 13.10.5Input Resistances of the Common Emitter and CommonSource Ampliers863 13.10.6CommonEmitter and CommonSource Output Resistances866 13.10.7Comparison of the Three Amplier Examples872 13.11CommonEmitter and CommonSource Amplier Summary872 13.11.1Guidelines for Neglecting the Transistor Output Resistance873 13.12Amplier Power and Signal Range873 13.12.1Power Dissipation873 13.12.2Signal Range874 Summary877 Key Terms878 Problems879 CHAPTER 14 SINGLETRANSISTOR AMPLIFIERS891 14.1Amplier Classication894 14.1.1Signal Injection and Extraction—the BJT894 14.1.2Signal Injection and Extraction—the FET895 14.1.3CommonEmitter (CE) and Common Source (CS)Ampliers896 14.1.4CommonCollector (CC) and Common Drain (CD)Topologies897 14.1.5CommonBase (CB) and Common Gate (CG)Ampliers899 14.1.6SmallSignal Model Review900 14.2Inverting Ampliers—CommonEmitter and CommonSource Circuits900 14.2.1The CommonEmitter (CE)Amplier900 14.2.2CommonEmitter Example Comparison913 14.2.3The CommonSource Amplier913 14.2.4SmallSignal Limit for the CommonSource Amplier916 14.2.5CommonEmitter and CommonSource Amplier Characteristics920 14.2.6CE/CS Amplier Summary921 14.2.7Equivalent Transistor Representation of the Generalized CE/CS Transistor921 14.3Follower Circuits—CommonCollector and CommonDrain Ampliers922 14.3.1Terminal Voltage Gain922 14.3.2Input Resistance923 14.3.3Signal Source Voltage Gain924 14.3.4Follower Signal Range924 14.3.5Follower Output Resistance925 14.3.6Current Gain926 14.3.7CC/CD Amplier Summary926 14.4Noninverting Ampliers—CommonBase and CommonGate Circuits930 14.4.1Terminal Voltage Gain and Input Resistance931 14.4.2Signal Source Voltage Gain932 14.4.3Input Signal Range933 14.4.4Resistance at the Collector and Drain Terminals933 14.4.5Current Gain934 14.4.6Overall Input and Output Resistances for the Noninverting Ampliers935 14.4.7CB/CG Amplier Summary938 14.5Amplier Prototype Review and Comparison939 14.5.1The BJT Ampliers939 14.5.2The FET Ampliers941 14.6CommonSource Ampliers Using MOS Inverters943 14.6.1Voltage Gain Estimate944 14.6.2Detailed Analysis945 14.6.3Alternative Loads946 14.6.4Input and Output Resistances947 14.7Coupling and Bypass Capacitor Design950 14.7.1CommonEmitter and Common Source Ampliers950 14.7.2CommonCollector and Common Drain Ampliers955 14.7.3CommonBase and CommonGate Ampliers957 14.7.4Setting Lower Cutoff Frequency fL960 14.8Amplier Design Examples961 14.8.1Monte Carlo Evaluation of the Common Base Amplier Design970 14.9Multistage acCoupled Ampliers975 14.9.1A ThreeStage acCoupled Amplier975 14.9.2Voltage Gain977 14.9.3Input Resistance979 14.9.4Signal Source Voltage Gain979 14.9.5Output Resistance979 14.9.6Current and Power Gain980 14.9.7Input Signal Range981 14.9.8Estimating the Lower Cutoff Frequency of the Multistage Amplier984 Summary986 Key Terms987 Additional Reading988 Problems988 CHAPTER 15 DIFFERENTIAL AMPLIFIERS AND OPERATIONAL AMPLIFIER DESIGN1004 15.1Differential Ampliers1007 15.1.1Bipolar and MOS Differential Ampliers1007 15.1.2dc Analysis of the Bipolar Differential Amplier1008 15.1.3Transfer Characteristic for the Bipolar Differential Amplier1010 15.1.4ac Analysis of the Bipolar Differential Amplier1011 15.1.5DifferentialMode Gain and Input and Output Resistances1012 15.1.6CommonMode Gain and Input Resistance1014 15.1.7CommonMode Rejection Ratio (CMRR)1016 15.1.8Analysis Using Differential and CommonMode HalfCircuits1017 15.1.9Biasing with Electronic Current Sources1020 15.1.10Modeling the Electronic Current Source in SPICE1021 15.1.11dc Analysis of the MOSFET Differential Amplier1021 15.1.12DifferentialMode Input Signals1024 15.1.13SmallSignal Transfer Characteristic for the MOS Differential Amplier1025 15.1.14CommonMode Input Signals1025 15.1.15Model for Differential Pairs1026 15.2Evolution to Basic Operational Ampliers1030 15.2.1A TwoStage Prototype for an Operational Amplier1031 15.2.2Improving the Op Amp Voltage Gain1036 15.2.3Darlington Pairs1037 15.2.4Output Resistance Reduction1038 15.2.5A CMOS Operational Amplier Prototype1042 15.2.6BiCMOS Ampliers1044 15.2.7All Transistor Implementations1044 15.3Output Stages1046 15.3.1The Source Follower—a ClassA Output Stage1046 15.3.2Efciency of ClassA Ampliers1047 15.3.3ClassB PushPull Output Stage1048 15.3.4ClassAB Ampliers1050 15.3.5ClassAB Output Stages for Operational Ampliers1051 15.3.6ShortCircuit Protection1051 15.3.7Transformer Coupling1053 15.4Electronic Current Sources1056 15.4.1SingleTransistor Current Sources1057 15.4.2Figure of Merit for Current Sources1057 15.4.3Higher Output Resistance Sources1058 15.4.4Current Source Design Examples1059 Summary1067 Key Terms1068 References1069 Additional Reading1069 Problems1069 CHAPTER 16 ANALOG INTEGRATED CIRCUIT DESIGN TECHNIQUES1087 16.1Circuit Element Matching1090 16.2Current Mirrors1091 16.2.1dc Analysis of the MOS Transistor Current Mirror1092 16.2.2Changing the MOS Mirror Ratio1094 16.2.3dc Analysis of the Bipolar Transistor Current Mirror1095 16.2.4Altering the BJT Current Mirror Ratio1097 16.2.5Multiple Current Sources1098 16.2.6Buffered Current Mirror1099 16.2.7Output Resistance of the Current Mirrors1100 16.2.8TwoPort Model for the Current Mirror1101 16.2.9The Widlar Current Source1103 16.2.10The MOS Version of the Widlar Source1106 16.3HighOutputResistance Current Mirrors1106 16.3.1The Wilson Current Sources1107 16.3.2Output Resistance of the Wilson Source1108 16.3.3Cascode Current Sources1109 16.3.4Output Resistance of the Cascode Sources1110 16.3.5Regulated Cascode Current Source1111 16.3.6Current Mirror Summary1112 16.4Reference Current Generation1115 16.5SupplyIndependent Biasing1116 16.5.1A VBE Based Reference1116 16.5.2The Widlar Source1116 16.5.3PowerSupplyIndependent Bias Cell1117 16.5.4A SupplyIndependent MOS Reference Cell1118 16.6The Bandgap Reference1120 16.7The Current Mirror as an Active Load1124 16.7.1CMOS Differential Amplier with Active Load1124 16.7.2Bipolar Differential Amplier with Active Load1131 16.8Active Loads in Operational Ampliers1135 16.8.1CMOS Op Amp Voltage Gain1135 16.8.2dc Design Considerations1136 16.8.3Bipolar Operational Ampliers1138 16.8.4Input Stage Breakdown1139 16.9The μA741Operational Amplier1140 16.9.1Overall Circuit Operation1140 16.9.2Bias Circuitry1141 16.9.3dc Analysis of the 741 Input Stage1142 16.9.4ac Analysis of the 741 Input Stage1145 16.9.5Voltage Gain of the Complete Amplier1146 16.9.6The 741 Output Stage1150 16.9.7Output Resistance1152 16.9.8ShortCircuit Protection1152 16.9.9Summary of the μA741 Operational Amplier Characteristics1152 16.10The Gilbert Analog Multiplier1153 Summary1155 Key Terms1156 References1157 Problems1157 CHAPTER 17 AMPLIFIER FREQUENCY RESPONSE1173 17.1Amplier Frequency Response1176 17.1.1LowFrequency Response1177 17.1.2Estimating ωL in the Absence of a Dominant Pole1177 17.1.3HighFrequency Response1180 17.1.4Estimating ωH in the Absence of a Dominant Pole1180 17.2Direct Determination of the LowFrequency Poles and Zeros—the CommonSource Amplier1181 17.3Estimation of ωL Using the ShortCircuit Time Constant Method1186 17.3.1Estimate of ωL for the Common Emitter Amplier1187 17.3.2Estimate of ωL for the CommonSource Amplier1191 17.3.3Estimate of ωL for the CommonBase Amplier1192 17.3.4Estimate of ωL for the CommonGate Amplier1193 17.3.5Estimate of ωL for the Common Collector Amplier1194 17.3.6Estimate of ωL for the CommonDrain Amplier1194 17.4Transistor Models at High Frequencies1195 17.4.1FrequencyDependent HybridPi Model for the Bipolar Transistor1195 17.4.2Modeling Cπ and Cμ in SPICE1196 17.4.3UnityGain Frequency fT1196 17.4.4HighFrequency Model for the FET1199 17.4.5Modeling CGS and CGD in SPICE1200 17.4.6Channel Length Dependence of fT1200 17.4.7Limitations of the HighFrequency Models1202 17.5Base and Gate Resistances in the SmallSignal Models1202 17.5.1Effect of Base and Gate Resistances on Midband Ampliers1203 17.6HighFrequency CommonEmitter and Common Source Amplier Analysis1204 17.6.1The Miller Effect1206 17.6.2CommonEmitter and CommonSource Amplier HighFrequency Response1208 17.6.3Direct Analysis of the Common Emitter Transfer Characteristic1210 17.6.4Poles of the CommonEmitter Amplier1211 17.6.5Dominant Pole for the CommonSource Amplier1214 17.6.6Estimation of ωH Using the Open Circuit TimeConstant Method1216 17.6.7CommonSource Amplier with Source Degeneration Resistance1217 17.6.8Poles of the CommonEmitter with Emitter Degeneration Resistance1219 17.7CommonBase and CommonGate Amplier HighFrequency Response1222 17.8CommonCollector and CommonDrain Amplier HighFrequency Response1224 17.8.1Frequency Response of the Complementary Emitter Follower1227 17.9SingleStage Amplier HighFrequency Response Summary1228 17.9.1Amplier GainBandwidth Limitations1229 17.10Frequency Response of Multistage Ampliers1230 17.10.1Differential Amplier1230 17.10.2The CommonCollector/Common Base Cascade1232 17.10.3HighFrequency Response of the Cascode Amplier1233 17.10.4Cutoff Frequency for the Current Mirror1234 17.10.5ThreeStage Amplier Example1235 17.11Introduction to Radio Frequency Circuits1243 17.11.1Radio Frequency Ampliers1244 17.11.2The ShuntPeaked Amplier1244 17.11.3SingleTuned Amplier1246 17.11.4Use of a Tapped Inductor—the Auto Transformer1248 17.11.5Multiple Tuned Circuits—Synchronous and Stagger Tuning1250 17.11.6CommonSource Amplier with Inductive Degeneration1251 17.12Mixers and Balanced Modulators1255 17.12.1Introduction to Mixer Operation1255 17.12.2A SingleBalanced Mixer1256 17.12.3The Differential Pair as a Single Balanced Mixer1257 17.12.4A DoubleBalanced Mixer1259 17.12.5The JONES Mixer—a Double Balanced Mixer/Modulator1261 Summary1265 Key Terms1266 References1266 Problems 1267 CHAPTER 18 TRANSISTOR FEEDBACK AMPLIFIERS AND OSCILLATORS1281 18.1Basic Feedback System Review1284 18.1.1ClosedLoop Gain1284 18.1.2ClosedLoop Impedances1285 18.1.3Feedback Effects1285 18.2Feedback Amplier Analysis at Midband1287 18.2.1ClosedLoop Gain1287 18.2.2Input Resistance1288 18.2.3Output Resistance1288 18.2.4Offset Voltage Calculation1289 18.3Feedback Amplier Circuit Examples1290 18.3.1SeriesShunt Feedback—Voltage Ampliers1290 18.3.2Differential Input SeriesShunt Voltage Amplier1295 18.3.3ShuntShunt Feedback—Transresistance Ampliers1298 18.3.4SeriesSeries Feedback— Transconductance Ampliers1304 18.3.5ShuntSeries Feedback—Current Ampliers1307 18.4Review of Feedback Amplier Stability1310 18.4.1ClosedLoop Response of the Uncompensated Amplier1311 18.4.2Phase Margin1312 18.4.3Higher Order Effects1316 18.4.4Response of the Compensated Amplier1317 18.4.5SmallSignal Limitations1319 18.5SinglePole Operational Amplier Compensation1319 18.5.1ThreeStage OpAmp Analysis1320 18.5.2Transmission Zeros in FET Op Amps1322 18.5.3Bipolar Amplier Compensation1323 18.5.4Slew Rate of the Operational Amplier1324 18.5.5Relationships between Slew Rate and GainBandwidth Product1325 18.6HighFrequency Oscillators1334 18.6.1The Colpitts Oscillator1335 18.6.2The Hartley Oscillator1336 18.6.3Amplitude Stabilization in LC Oscillators1337 18.6.4Negative Resistance in Oscillators1337 18.6.5Negative Gm Oscillator1338 18.6.6Crystal Oscillators1340 Summary1344 Key Terms1346 References1346 Problems1346 APPENDICES AStandard Discrete Component Values1359 BSolidState Device Models and SPICE Simulation Parameters1362 CTwoPort Review1367 前言 内容提要 第一部分 固态电子学与器件 第1章 电子学简介 1.1电子学发展简史： 从真空管到吉规模集成电路 1.2电信号的分类 1.2.1数字信号 1.2.2模拟信号 1.2.3A/D和D/A转换器——模拟与数字 信号的桥梁 1.3符号约定 1.4问题求解的方法 1.5电路理论的主要概念 1.5.1分压和分流 1.5.2戴维南定理和诺顿定理 1.6电信号的频谱 1.7放大器 1.7.1理想运算放大器 1.7.2放大器频率响应 1.8电路设计中元件参数的变化 1.8.1容差的数学模型 1.8.2最差情况分析 1.8.3蒙特卡洛分析 1.8.4温度系数 1.9数值精度 小结 关键词 参考文献 扩展阅读 习题 第2章 固态电子学 2.1固态电子材料 2.2共价键模型 2.3半导体中的漂移电流和迁移率 2.3.1漂移电流 2.3.2迁移率 2.3.3速度饱和 2.4本征硅的电阻率 2.5半导体中的杂质 2.5.1硅中的施主杂质 2.5.2硅中的受主杂质 2.6掺杂半导体中的电子和空穴浓度 2.6.1n型材料(ND>NA) 2.6.2p型材料(NA>ND) 2.7掺杂半导体中的迁移率和电阻率 2.8扩散电流 2.9总电流 2.10能带模型 2.10.1本征半导体中电子空穴对的产生 2.10.2掺杂半导体的能带模型 2.10.3补偿半导体 2.11集成电路制造综述 小结 关键词 参考文献 补充阅读 习题 第3章 固态二极管和二极管电路 3.1pn结二极管 3.1.1pn结静电学 3.1.2二极管内部电流 3.2二极管的iv特性 3.3二极管方程：二极管的数学模型 3.4二极管特性之反偏、零偏和正偏 3.4.1反偏 3.4.2零偏 3.4.3正偏 3.5二极管的温度系数 3.6反偏下的二极管 3.6.1实际二极管的饱和电流 3.6.2反向击穿 3.6.3击穿区的二极管模型 3.7pn结电容 3.7.1反偏 3.7.2正偏 3.8肖特基势垒二极管 3.9二极管的SPICE模型及版图 3.9.1二极管的版图 3.10二极管电路分析 3.10.1负载线分析法 3.10.2二极管数学模型分析法 3.10.3理想二极管模型 3.10.4恒压降模型 3.10.5模型比较与讨论 3.11多二极管电路 3.12二极管工作在击穿区域的分析 3.12.1负载线分析 3.12.2分段线性模型分析 3.12.3稳压器 3.12.4包含齐纳电阻的电路分析 3.12.5线性调整率和负载调整率 3.13半波整流电路 3.13.1带负载电阻的半波整流器 3.13.2整流滤波电容 3.13.3带RC负载的半波整流器 3.13.4纹波电压和导通期 3.13.5二极管电流 3.13.6浪涌电流 3.13.7额定峰值反向电压 3.13.8二极管功耗 3.13.9输出负电压的半波整流器 3.14全波整流电路 3.14.1输出负电压的全波整流器 3.15全波桥式整流 3.16整流器的比较及折中设计 3.17二极管的动态开关行为 3.18光电二极管、太阳能电池和发光二极管 3.18.1光电二极管和光探测器 3.18.2太阳能电池 3.18.3发光二极管（LED） 小结 关键词 参考文献 扩展阅读 习题 第4章 场效应晶体管 4.1MOS电容特性 4.1.1积累区 4.1.2耗尽区 4.1.3反型区 4.2NMOS晶体管 4.2.1NMOS晶体管的iv特性的定性描述 4.2.2NMOS晶体管的线性区特性 4.2.3导通电阻 4.2.4跨导 4.2.5iv特性的饱和 4.2.6饱和（夹断）区的数学模型 4.2.7饱和跨导 4.2.8沟道长度调制 4.2.9传输特性及耗尽型MOSFET 4.2.10体效应或衬底灵敏度 4.3PMOS晶体管 4.4MOSFET电路符号 4.5MOS晶体管的电容 4.5.1NMOS晶体管的线性区电容 4.5.2饱和区电容 4.5.3截止区电容 4.6SPICE中的MOSFET建模 4.7MOS晶体管的等比例缩放 4.7.1漏极电流 4.7.2栅极电容 4.7.3电流和功率密度 4.7.4功耗延迟积 4.7.5截止频率 4.7.6大电场限制 4.7.7包含高场限制的统一MOS晶体管模型 4.7.8亚阈值导通 4.8MOS晶体管的制造工艺及版图设计规则 4.8.1最小特征尺寸和对准容差 4.8.2MOS晶体管的版图 4.9NMOS场效应管的偏置 4.9.1为什么需要偏置 4.9.2四电阻偏置 4.9.3恒定栅源电压偏置 4.9.4Q点的图形分析 4.9.5包含体效应的分析 4.9.6使用统一模型进行分析 4.10PMOS场效应晶体管的偏置 4.11结型场效应管（JFET） 4.11.1偏压下的JFET 4.11.2漏源偏置下的JFET沟道 4.11.3n沟道JFET的iv特性 4.11.4p沟道JFET 4.11.5JFET的电路符号和模型小结 4.11.6JFET电容 4.12JFET的SPICE模型 4.13JFET和耗尽型MOSFET的偏置 小结 关键词 参考文献 习题 第5章 双极型晶体管 5.1双极型晶体管的物理结构 5.2npn晶体管的传输模型 5.2.1正向特性 5.2.2反向特性 5.2.3任意偏置条件下晶体管传输模型方程 5.3pnp晶体管 5.4晶体管传输模型的等效电路 5.5双极型晶体管的iv特性 5.5.1输出特性 5.5.2传输特性 5.6双极型晶体管的工作区 5.7传输模型的简化 5.7.1截止区的简化模型 5.7.2正向有源区的模型简化 5.7.3双极型集成电路中的二极管 5.7.4反向有源区的简化模型 5.7.5饱和区模型 5.8双极型晶体管的非理想特性 5.8.1结击穿电压 5.8.2基区的少数载流子传输 5.8.3基区传输时间 5.8.4扩散电容 5.8.5共发电流增益对频率的依赖性 5.8.6Early效应和Early电压 5.8.7Early效应的建模 5.8.8Early效应的产生原因 5.9跨导 5.10双极型工艺与SPICE模型 5.10.1定量描述 5.10.2SPICE模型方程 5.10.3高性能双极型晶体管 5.11BJT的实际偏置电路 5.11.1四电阻偏置网络 5.11.2四电阻偏置网络的设计目标 5.11.3四电阻偏置电路的迭代分析 5.12偏置电路的容差 5.12.1最差情况分析 5.12.2蒙特卡洛分析 小结 关键词 参考文献 习题 第二部分 数字电路 第6章 数字电路简介 6.1理想逻辑门 6.2逻辑电平定义和噪声容限 6.2.1逻辑电压电平 6.2.2噪声容限 6.2.3逻辑门的设计目标 6.3逻辑门的动态响应 6.3.1上升和下降时间 6.3.2传输延迟 6.3.3功耗延迟积 6.4布尔代数回顾 6.5NMOS逻辑设计 6.5.1带负载电阻的NMOS反相器 6.5.2开关晶体管MS的W/L比设计 6.5.3负载电阻设计 6.5.4负载线的可视化 6.5.5开关器件的导通电阻 6.5.6噪声容限分析 6.5.7VIL和VOH的计算 6.5.8 VIH和VOL的计算 6.5.9电阻器负载反相器噪声容限 6.5.10负载电阻问题 6.6晶体管替代负载电阻方案 6.6.1NMOS饱和负载反相器 6.6.2带线性负载设备的NMOS反相器 6.6.3带耗尽型负载的NMOS反相器 6.7NMOS反相器小结与比较 6.8速度饱和对静态设计的影响 6.8.1开关晶体管设计 6.8.2负载晶体管设计 6.8.3速度饱和影响小结 6.9NMOS与非门和或非门 6.9.1或非门 6.9.2与非门 6.9.3NMOS耗尽型工艺中的或非门及与 非门布局 6.10复杂NMOS逻辑设计 6.11功耗 6.11.1静态功耗 6.11.2动态功耗 6.11.3MOS逻辑门的功率缩放 6.12MOS逻辑门的动态特性 6.12.1逻辑电路中的电容 6.12.2带电阻性负载的NMOS反相器的 动态响应 6.12.3NMOS反相器延迟比较 6.12.4速度饱和对反相器延迟的影响 6.12.5基于参考电路仿真的缩放 6.12.6固有门延迟的环形振荡器测量法 6.12.7无负载反相器的延迟 6.13PMOS逻辑 6.13.1PMOS反相器 6.13.2与非门和或非门 小结 关键词 参考文献 补充阅读 习题 第7章 CMOS逻辑电路设计 7.1CMOS反相器 7.1.1CMOS反相器版图 7.2CMOS反相器的静态特性 7.2.1CMOS电压传输特性 7.2.2CMOS反相器的噪声容限 7.3CMOS反相器的动态特性 7.3.1传播延迟估计 7.3.2上升和下降时间 7.3.3按性能等比例缩放 7.3.4速度饱和效应对CMOS反相器延迟的 影响 7.3.5级联反相器延迟 7.4CMOS功耗及功耗延迟积 7.4.1静态功耗 7.4.2动态功耗 7.4.3功耗延迟积 7.5CMOS或非门和与非门 7.5.1CMOS或非门 7.5.2CMOS与非门 7.6CMOS复杂门电路设计 7.7逻辑门的最小尺寸设计及性能 7.8级联缓冲器 7.8.1级联缓冲器延迟模型 7.8.2最优级数 7.9CMOS传输门 7.10双稳态电路 7.10.1双稳态锁存器 7.10.2RS触发器 7.10.3采用传输门的D锁存器 7.10.4主从D触发器 7.11CMOS闩锁效应 小结 关键词 参考文献 扩展阅读 习题 第8章 MOS存储器及其电路 8.1随机存取存储器（RAM） 8.1.1RAM存储器架构 8.1.2256MB存储器芯片 8.2静态存储器单元电路 8.2.1内存单元的隔离和访问6T单元 8.2.2读操作 8.2.3向6T单元写数据 8.3动态存储单元电路 8.3.11T单元电路 8.3.21T单元的数据存储 8.3.31T单元的数据读取 8.3.44T单元电路 8.4感测放大器 8.4.16T单元的感测放大器 8.4.21T单元的感测放大器 8.4.3升压字线电路 8.4.4钟控CMOS感测放大器 8.5地址译码器 8.5.1或非门译码器 8.5.2与非门译码器 8.5.3传输管列译码器 8.6只读存储器(ROM) 8.7闪存 8.7.1浮栅技术 8.7.2NOR电路实现 8.7.3NAND电路实现 小结 关键词 参考文献 习题 第9章 双极型逻辑电路 9.1电流开关(发射极耦合对) 9.1.1电流开关静态特性的数学模型 9.1.2对于VI>VREF的电流开关分析 9.1.3VI